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Ahmed Louri

Headshot of Ahmed Louri

Ahmed Louri

David and Marilyn Karlgaard Professor of Electrical and Computer Engineering

Department: Electrical and Computer Engineering

Contact:

Email: Ahmed Louri
Office Phone: (202) 994-8241
HPCAT lab website: https://hpcat.seas.gwu.edu/
SEH 5560 | Office hours: T: 3:30 – 4:30 pm

Dr. Ahmed Louri is the David and Marilyn Karlgaard Endowed Chair Professor of Electrical and Computer Engineering at George Washington University, which he joined in August 2015. He is also the Director of the High-Performance Computing Architectures and Technologies Laboratory (HPCAT, https://hpcat.seas.gwu.edu/). Dr. Louri received a Ph.D. degree in Computer Engineering from the University of Southern California, Los Angeles, California in 1988. From 1988 to 2015, he was a Professor of Electrical and Computer Engineering at the University of Arizona, and during that time, he served six years (2000 to 2006) as the Chair of the Computer Engineering Program.  From 2010 to 2013, Dr. Louri served as a program director in the National Science Foundation's (NSF) Directorate for Computer and Information Science and Engineering. He directed the core computer architecture program and was on the management team of several cross-cutting programs, including Cyber-Physical Systems; Expeditions in Computing; Computing Research Infrastructure; Secure and Trustworthy Cyberspace; Failure-Resistant Systems, Science Engineering and Education for Sustainability; Cyber-Discovery Initiative, among others. While at NSF, Dr. Louri initiated multidisciplinary research programs in several key areas of computer architecture, high-performance computing, sustainability, emerging technologies, resiliency, and security.

Dr. Louri conducts research in the broad area of computer architecture and parallel computing, with emphasis on interconnection networks, scalable parallel computing systems, versatile and flexible computing systems, and power-efficient, reliable, and secure Network-on-Chips (NoCs) for multicore architectures. Recently, he has been concentrating on energy-efficient, reliable, and high-performance many-core architectures; accelerator-rich reconfigurable heterogeneous architectures; secure network-on-chips for multicores and SoCs; approximate computing and communications; machine learning techniques for efficient computing, memory, and interconnect systems; heterogeneous manycore architectures & chiplet-based designs; emerging interconnect technologies (photonic, wireless, RF, hybrid) for multi-core architectures and chip multiprocessors (CMPs); future parallel computing models and architectures (including convolutional neural networks, deep neural networks, and approximate computing); cloud-computing and data centers. He has published more than 200 refereed journal articles and peer-reviewed conference papers and is the inventor of several US and international patents. His early work explored optics’ unique properties to advance computing and communications. He was instrumental in bringing optical interconnects into mainstream research in computing and played a critical role in bridging the gap between the computer architecture and optics research communities. He received the Best Article Award from IEEE Micro and was runner-up for the Best Paper Award at several conferences.

Dr. Louri is a Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE), a member of the IEEE Computer Society (CS) Technical Committee on Computer Architecture, the IEEE CS Technical Committee on Parallel Processing, the IEEE CS Technical Committee on Microprocessors & Microcomputers, and the Optical Society of America. Dr. Louri is the recipient of the IEEE Computer Society 2020 Edward J. McCluskey Technical Achievement Award, "for pioneering contributions to the solution of on-chip and off-chip communication problems for parallel computing and manycore architectures.” The IEEE Computer Society Edward J. McCluskey Technical Achievement Award is given for outstanding and innovative contributions to the fields of computer and information science and engineering or computer technology, usually within the past 10 to 15 years. Contributions must have significantly promoted technical progress in the field. https://www.computer.org/profiles/ahmed-louri. IEEE has made a video of the award which can be seen at the following link: https://youtu.be/W-ejXgVxV9c. He is also the recipient of the Office of Vice President for Research Distinguished Researcher Award, George Washington University, 2021. This award is given to one scholar who has made significant contributions in research and scholarship to the university and society. He is also the recipient of the NSF CAREER Award, the Advanced Telecommunications Organization of Japan Fellowship, the CNRS Research Excellence Fellowship, the Japan Society for the Promotion of Science Fellowship, and the NSF Outstanding Service Award in recognition of his outstanding service to the field of computing and the research community.

Dr. Louri served as the program area chair of the 34th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2020), the general chair for the 25th IEEE CS Annual Symposium of the High-Performance Computer Architecture (HPCA 2019), the general chair of the 21st IEEE International Conference on High-Performance Computing and Communications (HPCC 2019), the general chair of the 13th IEEE CS Annual Symposium of the High-Performance Computer Architecture (HPCA 2007), the general co-chair of the Second Workshop on Optics in Communications and Computer Sciences (1999), and the general chair for the Workshop on Optics in High-Performance Computing Systems (1996). For over 30 years, Dr. Louri has served and continues to serve on the executive and technical program committees of numerous international conferences. He has served as a reviewer and panelist of funding agencies, including NSF, DARPA, DOE, AFOSR, Agence Nationale de la Recherche (France), Qatar National Research Foundation, Hong Kong National Research Council, European Research Council, among several others. He consults for industry and is often invited to be the keynote speaker at various conferences.

Dr. Louri is the Editor-in-Chief of the IEEE Transactions on Sustainable Computing (TSUSC) (2025 - ). TSUSC (a joint publication between IEEE Computer Society and IEEE Communications Society, with Technical Sponsorship from the IEEE Council Electronic Design Automation (CEDA)) is a peer-reviewed journal devoted to publishing high-quality papers that explore the different aspects of sustainable computing over a wide range of problem domains and technologies from software and hardware designs to applications. Dr. Louri served as the Editor-in-Chief of the IEEE Transactions on Computers, the flagship journal of the IEEE Computer Society (CS) for five years, January 2019 – December 2023. Dr. Louri also served as associate editor of IEEE Transactions on Cloud Computing (2020 – ). Dr. Louri’s other IEEE committee service includes being: 2024 IEEE Computer Society (CS) Transactions Operations Committee (TOC) Chair, member of the CS Board of Governors (2024), Chair for the IEEE CS Fellow Evaluation Committee (2019), Chair for the IEEE Computer Architecture Letters Editor-in-Chief Search Committee (2021), Chair for the IEEE Transactions on Cloud Computing Editor-in-Chief Search Committee (2019 and 2025), Vice-chair for the IEEE CS Fellow Evaluation Committee (2013, 2017, 2018, 2021 and 2025) and member of the IEEE Fellow Evaluation Committee (2022-2024), among several others.

  • Ph.D. 1988, University of Southern California, Los Angeles, California
  • Computer Architecture And High Performance Computing
  • Accelerator Design for AI and ML Applications
  • Graph Neural Network Accelerator Design
  • Hardware-Software Co-optimization for Domain-specific Architectures
  • Sustainable Computing
  • Network-on-chips and Emerging Interconnect Technologies
  • Approximate Computing and Communications
  • Energy-Efficient Computing Systems
  • Scalable and Resilient Parallel Architectures

Selected Publications (Since 2023):

  1. Y. Chen, A. Louri, S. Liu, and F. Lombardi, “Approximate Communication in Network-on-Chips for Training and Inference of Image Classification Models,” in Design and Applications of Emerging Computer Systems, W. Liu, J. Han, and F. Lombardi, Eds., Cham: Springer Nature Switzerland, 2024, pp. 709–740.
  2. Jiaqi Yang, Hao Zheng, and Ahmed Louri. “DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference.” to appear in Proceedings of IEEE International Symposium on Computer Architecture (ISCA), Tokyo, Japan, June 21-25, 2025.
  3. Jiaqi Yang, Hao Zheng, and Ahmed Louri, “I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators,” in Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, Nevada, March 1 – 5, 2025.
  4. Yingnan Zhao, Ke Wang, and Ahmed Louri, "A High-performance and Flexible Accelerator for Dynamic Graph Convolutional Networks," in Proceedings of the Design Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, March 31-April 2, 2025.
  5. Yingnan Zhao, Ke Wang, and Ahmed Louri, “An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference,” in Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 23 – 27, 2024.
  6. Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, and Hao Zheng, “VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design,” in Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 23 – 27, 2024.
  7. Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Aurora: A Versatile and Flexible Accelerator for Generic Graph Neural Networks,” in Proceedings of the IEEE International Parallel & Distributed Processing Symposium (IPDPS), San Francisco, CA, USA, May 27 – May 31, 2024.
  8. Juliana Curry, Ahmed Louri, Avinash Karanth, and Razvan Bunescu, "PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices," in Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), San Francisco, CA, USA, May 27-31, 2024.
  9. Juliana Curry, Ahmed Louri, Avinash Karanth, and Razvan Bunescu, "Reconfigurable PCM-based photonic accelerator for energy-efficient DNN inference and training,” in Proceedings of the Society of Photo-Optical Instrumentation Engineers (SPIE)  PC13113, Photonic Computing: From Materials and Devices to Systems and Applications, PC131130L, San Diego, CA, USA, October 3, 2024.
  10. Yuan Li, Ahmed Louri, and Avinash Karanth, “A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration,” in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 35, no. 1, pp. 46-58, January 2024.
  11. Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration,” in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 35, no. 2, pp. 349-361, February 2024.
  12. Yuechen Chen, Ahmed Louri, Fabrizio Lombardi, and Shanshan Liu, “Chiplet-GAN: Chiplet-based Accelerator Design for Scalable Generative Adversarial Network Inference,” in IEEE Circuits and System (TCAS), vol. 23, issue 3, pp. 19-33, August 2024.
  13. Yuechen Chen, Ahmed Louri, Shanshan Liu, and Fabrizio Lombardi, “A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 10, pp. 4638 - 4651, July 2024.
  14. Yuan Li, Ahmed Louri, and Avinash Karanth, "MERIT: A Sustainable DNN Accelerator Design with Photonic Phase-Change Memory," in IEEE Transactions on Sustainable Computing (TSUSC), early access, pp. 1-12, December 2024.
  15. Yingnan Zhao, Ke Wang, and Ahmed Louri, "OPT-GCN: A Unified and Scalable Chiplet-based Accelerator for High-Performance and Energy-Efficient GCN Computation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 12, pp. 4827 – 4840, December 2024.
  16. Ziheng Wang, Fabrizio Lombardi, Shanshan Liu, Pedro Reviriego, Ahmed Louri, and Fabrizio Lombardi, "Fault Tolerance in Triplet Network Training: Analysis, Evaluation, and Protection Methods,” in IEEE Transactions on Emerging Topics in Computing (TETC), early access, pp. 1-10, October 2024.
  17. Fabrizio Lombardi, Ziheng Wang, Shanshan Liu, Pedro Reviriego, Ahmed Louri, and Fabrizio Lombardi, "ASIC Design of Nanoscale Artificial Neural Networks for Inference/Training by Floating-Point Arithmetic,” in IEEE Transactions on Nanotechnology, vol. 23, pp. 208-216, February 2024.
  18. Jiaqi Yang, Hao Zheng, and Ahmed Louri, "Agile-GNN: A Versatile and Flexible GNN Accelerator for Efficient Execution of Diverse Graph Neural Network Models,” accepted in IEEE Transactions on Computers (TC), March 2024.
  19. Yingnan Zhao, Ke Wang, and Ahmed Louri, "HS-GCN: A High-performance, Sustainable, and Scalable Chiplet-based Accelerator for Graph Convolutional Network Inference," accepted in IEEE Transactions on Sustainable Computing (TSUSC), June 2024.
  20. Youssef Alama, Sampada Sakpal, Ke Wang, Razvan Bunescu, Avinash Karanth, and Ahmed Louri. "Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults." arXiv preprint arXiv:2412.16208, December 2024.
  21. Ke Wang, Hao Zheng, Jiajun Li, and Ahmed Louri, "Morph-GCNX: A Universal Architecture for High-performance and Energy-efficient Graph Convolutional Network Acceleration", in IEEE Transactions on Sustainable Computing, doi: 10.1109/TSUSC.2023.3313880, 2023.
  22. Jiajun Li, Ke Wang, Hao Zheng, and Ahmed Louri, “GShuttle: Optimizing Memory Access for Graph Convolutional Neural Network Accelerators,” in Journal of Computer Science and Technology, vol. 38, no. 1, pp. 115 – 127, February 2023.
  23. Yuechen Chen, Ahmed Louri, Shanshan Liu, and Fabrizio Lombardi, “Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips,” in IEEE Transactions on Sustainable Computing, vol. 8, no. 1, pp. 120 – 132, January 2023.
  24. Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, and Fabrizio Lombardi, “Error-Resillient Data Compression with Tunstall Codes,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 1963 – 1975, May 2023.
  25. Yuechen Chen, Shanshan Liu, Fabrizio Lombardi, and Ahmed Louri, “A Technique for Approximate Communication in Network-on-Chips for Image Classification”, IEEE Transactions on Emerging Topics in Computing (TETC), vol. 11, no. 1, pp. 30-42, January 2023.
  26. Farzad Niknia, Ziheng Wang, Shanshan Liu, Pedro Reviriego, Ahmed Louri, and Fabrizio Lombardi, “Floating-Point Formats and Arithmetic for Highly Accurate Multi-Layer Perceptrons,” in Proceedings of the IEEE International Conference on Nanotechnology (NANO), Jeju City, Korea, July 2-5, 2023.
  27. Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, and Hao Zheng, "Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration", in Proceedings of the IEEE International Conference on Computer Design (ICCD), Washington DC, November 6 – 8, 2023.
  28. Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, and Hao Zheng, “ARIES: Accelerating DNN Training in Chiplet-based Systems via Flexible Interconnects,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, October 29-November 2, 2023.
  29. Yuan Li, Ahmed Louri, and Avinash Karanth, “A Silicon Photonic Multi-DNN Accelerator,” in Proceedings of the IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, October 21 – 25, 2023.
  30. Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications,” in Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 9 – 13, 2023.
  31. Kyle Shiflett, Avinash Karanth, Razvan Bunescu, and Ahmed Louri, “Flumen: Dynamic Processing in the Photonic Interconnect,” in Proceedings of ACM/IEEE International Symposium on Computer Architecture (ISCA), Orlando, FL, June 17 – 21, 2023.
  • Endowed Chair Professor of ECE, George Washington University, 2015
  • IEEE Life Fellow
  • IEEE Computer Society (CS) Golden Core Award, IEEE Computer Society, 2024
  • Edward J. McCluskey Technical Achievement Award, IEEE Computer Society, 2020
  • OVPR Distinguished Researcher Award, George Washington University, 2021
  • Fellow, Asia-Pacific Artificial Intelligence Association
  • Editor-in-Chief, IEEE Transactions on Sustainable Computing,  January 2025
  • Editor-in-Chief, IEEE Transactions on Computers, January 2019- 2023
  • National Academy of Inventors (NAI), George Washington University, 2023
  • IEEE Outstanding Leadership Award, IEEE Computer Society, 2019
  • Ke Wang, Hao Zheng, and Ahmed Louri. “Systems and Methods for Learning-Based High-Performance, Energy-Efficient, and Secure On-Chip Communication Design Framework.” U.S. Patent 20210342690A1, Granted, January 2025.
  • Jiajun Li and Ahmed Louri. “Systems and Methods for Compression and Acceleration of Convolutional Neural Networks.” U.S. Patent 12073306B2, Granted, August 2024.
  • Ke Wang and Ahmed Louri. “Learning-based high-performance, energy-efficient, fault-tolerant on-chip communication design framework.” U.S. Patent 12040897B2, Granted, July 2024.
  • Jiaqi Yang, Hao Zheng, and Ahmed Louri, “Venus: A Versatile Deep Neural Network Accelerator Design for Multiple Applications.” U.S. Patent 63665776,  Filed, January 2025.
  • Ahmed Louri, Hao Zheng “EZ-Pass and Energy-Efficient and High-Performance Router Architecture for Scalable Network-on-Chips,” Patent, 16/547,161, filed August 21, 2019.
  • Ahmed Louri, Hao Zheng, and Ke Wang, “Interconnection Network with Adaptable Router Lines for Chiplet-Based Manycore Architecture, ” Patent 17/085,454, filed October 2020.
  • Ahmed Louri, Ke Wang, and Hao Zheng, “Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework,”  Patent, No. 63/019,720,  Patent, filed May 2020
  • Ahmed Louri, Yuechen Chen, “Systems and Methods for Approximate Communication Framework for Networks-on-Chips,” Patent 17/307,745, filed May 2021.
  • Ahmed Louri, Jiajun Li, An Algorithm-hardware Co-Design Method for Efficient Machine Learning Applications, Provisional Patent, No. 17/551,967, filed December 2020.
  • Ahmed Louri, Jiajun Li, A Processor Design for Graph Convolutional Neural Network-based Machine Learning Applications, Provisional Patent, No. 17/551,876, filed December 2020.
  • Ahmed Louri and Yuan Li, “SPACX: A Hardware and Algorithm Co-Optimized Photonic Deep Neural Network Computing Architecture,” U.S. Provisional Patent, No. 63/456,255, May 2023.
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